KS8993MI SMI Integrated Flash Memory IC Chip 128 BFQFP 3 Port 10 / 100 Managed

KS8993MI MICREL INTEGRATED 3-PORT 10/100 MANAGED FLASH MEMORY IC CHIP 128-BFQFP

Quick Detail:

Integrated 3-Port 10/100 Managed Integrated 3-Port 10/100 Managed


Description:

The KS8993M, a highly integrated Layer 2 managed switch, is designed for low port count, cost-sensitive 10/100 Mbps switch systems. It offers an extensive feature set that includes tag/port-based VLAN, quality of service (QoS) priority, management, management information base (MIB) counters, MII/SNI, and CPU control/data interfaces to effectively address both current and emerging Fast Ethernet applications.
The KS8993M contains two 10/100 transceivers with patented mixed-signal low-power technology, three media access control (MAC) units, a high-speed non-blocking switch fabric, a dedicated address lookup engine, and an on-chip frame buffer memory.
Both PHY units support 10BASE-T and 100BASETX. In addition, one of the PHY unit supports 100BASE-FX.
The KS8993ML is the single supply version with all the identical rich features of the KS8993M.


Applications:

• Proven Integrated 3-Port 10/100 Ethernet Switch
– 2nd generation switch with three MACs and two PHYs fully compliant to IEEE 802.3u standard
– Non-blocking switch fabric assures fast packet
delivery by utilizing a 1K MAC address lookup table and a store-and-forward architecture
– Full duplex IEEE 802.3x flow control (pause) with force mode option
– Half-duplex back pressure flow control
– Automatic MDI/MDI-X crossover with disable and enable option
– 100BASE-FX support on port 1
– MII interface supports both MAC mode and PHY mode
– 7-wire serial network interface (SNI) support for legacy MAC
– Comprehensive LED Indicator support for link, activity, full/half duplex and 10/100 speed
• Comprehensive Configuration Register Access
– Serial management interface (SMI) to all internal registers
– MII management (MIIM) interface to PHY registers
– SPI and I2
C Interface to all internal registers
– I/0 Pins strapping and EEPROM to program selective registers in unmanaged switch mode
– Control registers configurable on the fly (portpriority, 802.1p/d/q, AN…)
• QoS/CoS Packet Prioritization Support
– Per port, 802.1p and DiffServ-based
– Re-mapping of 802.1p priority field per port basis
• Advanced Switch Features
– IEEE 802.1q VLAN support for up to 16 groups (full-range of VLAN ID)
– VLAN ID tag/untag options, per port basis
– IEEE 802.1p/q tag insertion or removal on a per port basis (egress)
– Programmable rate limiting from 0Mbps to
100Mbps at the ingress and egress port, rate options for high and low priority per port basis
– Broadcast storm protection with % control (global and per port basis)
– IEEE 802.1d spanning tree protocol support
– Upstream special tagging mode to inform the processor which ingress port receives the packet
– IGMP v1/v2 snooping support for multicast packet filtering
– Double-tagging support


Specifications: